The present invention relates to a method of manufacturing a semiconductor device comprising trench isolation. The invention has particular applicability in manufacturing high-density semiconductor devices with submicron design features and active regions isolated by narrow shallow insulated trenches.
Conventional semiconductor devices comprise a substrate and various electrically isolated regions, called active regions, in which individual circuit components are formed. The active regions typically comprise source/drain regions formed in the semiconductor substrate by implantation of impurities, spaced apart by a channel region on which a gate electrode is formed with a gate oxide layer therebetween. The gate electrode controls the turn-on and turn-off of each transistor.
The electrical isolation of these active regions is typically accomplished by thermal oxidation of the semiconductor substrate, typically monocrystalline silicon or an epitaxial layer formed thereon, bounding the active regions. One type of isolation structure is known as trench isolation, wherein shallow trenches are etched in the substrate, and an oxide liner is thermally grown on the trench walls. The trench is then refilled with an insulating material. The resulting structure is referred to as a shallow trench isolation (STI) structure.
A typical method of trench formation comprises initially growing a pad oxide layer on the substrate, and depositing a barrier nitride layer thereon. A photoresist mask is then applied to define the trench areas. The exposed portions of the nitride layer are then etched away, followed by the pad oxide layer. The etching continues into the substrate to form the shallow trench. When etching of the trench is completed, the photoresist is stripped off the nitride layer.
Next, the substrate is oxidized to form an oxide liner on the corners, walls and base of the trench to control the silicon-silicon dioxide interface quality and to round the trench edges where they meet the substrate main surface to improve subsequent gate oxide growth. The trench is then refilled with an insulating material (or xe2x80x9ctrench fillxe2x80x9d), such as silicon dioxide derived from tetraethyl orthosilicate (TEOS) deposited by low pressure chemical vapor deposition (LPCVD) or plasma enhanced chemical vapor deposition (PECVD), or a high density plasma (HDP) oxide. The surface is then planarized, as by chemical-mechanical polishing (CMP) using the barrier nitride layer as a polish stop, and the nitride and pad oxide are stripped off the active areas to complete the trench isolation structure.
Current demands for high density and performance associated with ultra large scale integration require submicron features of about 0.25 microns (xcexcm) and under, including ultranarrow STI trenches having widths of about 0.25 xcexcm or less and depths of up to 0.4 xcexcm. However, at such small trench widths, voids (i.e., seams) occur in the trench fill, adversely affecting the electrical characteristics of the finished devices. It is believed that voids occur due to the fact that these ultranarrow trenches tend to have vertical walls.
Prior attempts to reduce voids comprise lowering the oxide deposition rate, but this technique disadvantageously reduces production throughput by increasing the amount of time needed for the trench fill step. For example, oxide trench fill can be accomplished using high deposition rate technology such as PECVD and HDP, without voids, when the trench width is above about 0.4 xcexcm. However, at trench widths of about 0.35 xcexcm and below, PECVD techniques do not yield acceptable results (i.e., they form too many voids). Thus, for ultranarrow trenches, only a low deposition rate trench fill process such as LPCVD can be successfully employed. In addition to its low deposition rate, LPCVD methodology further reduces production throughput since it requires frequent maintenance. Moreover, at trench widths below about 0.3 xcexcm, all deposition processes produce voids in the trench fill of moderately deep trenches (i.e., trenches having a depth of about 0.4 xcexcm).
A further problem in STI formation is stress induced at the top corners (i.e. edges) of the trench and at the sidewalls of the trench when the trench is brought up to temperature ( typically about 1000xc2x0 C.) for the liner oxidation/edge-rounding step. This stress is transmitted to the active regions of the substrate, resulting in degradation of the quality of the gate oxide, which adversely affects the performance of the finished device. Stress transmitted to the active areas during STI formation becomes more severe as the width of active areas decreases; e.g., to below about 0.3 xcexcm.
The stress at the top corners of the trench is believed to be due to the high temperatures necessary for oxidation. The stress at the trench walls is believed due to a phenomenon known as xe2x80x9creentrancexe2x80x9d of the walls. Trench walls are conventionally formed having a preferred slope, e.g., about 70 to 75 degrees from the horizontal. However, during the oxidation step, the walls expand inwardly and tend to vertically align due to excessive oxidation of the trench wall relative to the adjacent active region, thereby inducing stress in the active region. This condition is called reentrance. The excessive oxidation occurs because the oxide grows faster on the trench walls than on the surface of the substrate, which has a different crystallographic orientation. Reentrance becomes more severe as the width of the trench is decreased below about 0.30 xcexcm, because ultranarrow trenches tend to have more vertical walls due to the difficulty in forming such trenches with the above-discussed preferred slope.
There exists a need for a method of manufacturing a semiconductor device having an STI structure with ultranarrow trenches without voids in the trench fill, which STI structure can be produced using a high deposition rate trench fill technique, thereby improving device performance and increasing production throughput. There also exists a continuing need for shallow trench isolation methodology that eliminates or significantly reduces stress and reentrance of the trench surface resulting from the oxidation step, thereby reducing stress in the active regions of the substrate and, hence, improving gate oxide quality.
An advantage of the present invention is a method of manufacturing a semiconductor device having insulated narrow trenches formed in a semiconductor substrate with substantially no voids in the insulating trench fill, using a high deposition rate process. A further advantage of the present invention is a method of manufacturing a semiconductor device having STI with reduced stress in the active regions of the substrate.
Additional advantages and other features of the present invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from the practice of the present invention. The advantages of the present invention may be realized and obtained as particularly pointed out in the appended claims.
According to the present invention, the foregoing and other advantages are achieved in part by a method of manufacturing a semiconductor device, which method comprises forming a narrow trench in a semiconductor substrate, the trench having an internal surface and having edges at a main surface of the substrate; depositing a spacer formation layer to cover the internal surface of the trench; anisotropically etching the spacer formation layer to form thin spacers on sidewalls of the internal surface of the trench; and depositing an insulating material to fill the trench substantially without creating voids.
Additional advantages of the present invention will become readily apparent to those skilled in this art from the following detailed description, wherein only the preferred embodiment of the present invention is shown and described, simply by way of illustration of the best mode contemplated for carrying out the present invention. As will be realized, the present invention is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects, all without departing from the present invention. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as restrictive.